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general description the max16997/max16998 are microprocessor (?) supervisory circuits for high-input-voltage and low-qui- escent-current applications. these devices detect downstream circuit failures and provide switchover to redundant circuitry. see the selector guide for the dif- ferent versions of this product family. the max16997/max16998 family has four independent inputs for reset and watchdog functions. swt and srt inputs independently set the timeout periods of watch- dog and reset timers through external capacitors. resetin/en monitor voltages at respective inputs. a resistive voltage-divider sets the reset threshold. the max16998a/b/d generate two output signals, reset and enable . reset asserts whenever resetin drops below its threshold voltage or when the watchdog timer detects a timing fault at wdi. once asserted, and after all reset conditions are removed, reset remains low for the reset timeout period, t reset , and then goes high. the max16997a generates one output signal ( enable ) based on the voltage level at en and the signal at wdi. the max16997a does not have a reset output. the watchdog is disabled if the voltage at en is below its threshold. the max16997a watchdog timer starts tim- ing when the voltage at en becomes higher than the preset threshold voltage level. each time en rises above the preset threshold voltage, the initial watchdog timeout period is 8 times the normal watchdog timeout period (t wp ). the max16997/max16998 are available in 8-pin lead- free ?ax packages and are fully specified over the -40? to +125? automotive temperature range. applications automotive industrial features wide 5v to 40v input voltage range 18 a quiescent current (typical at +125?) capacitor-adjustable timeout period for watchdog and reset windowed watchdog timer options (max16998b/d) external voltage monitoring (resetin for the max16998a/b/d and en for the max16997a) car battery-compatible en input ttl- and cmos-compatible open-drain outputs 18v maximum open-drain reset output voltage 28v maximum open-drain enable output voltage power-on/power-off reset functionality (max16998a/b/d only) aec-q100 qualified -40? to +125? operating temperature range small (3mm x 3mm) max package wdi narrow pulse immunity max16997/max16998 high-voltage watchdog timers with adjustable timeout delay ________________________________________________________________ maxim integrated products 1 part temp range pin-package max16997 aaua+ -40? to +125? 8 ?ax MAX16997AAUA/v+ -40? to +125? 8 ?ax max16998 aaua+ -40? to +125? 8 ?ax max16998aaua/v+ -40? to +125? 8 ?ax max16998baua+ -40? to +125? 8 ?ax max16998baua/v+ -40? to +125? 8 ?ax max16998daua+ -40? to +125? 8 ?ax max16998daua/v+ -40? to +125? 8 ?ax part watchdog window size (%) enable reset en resetin max16997a 100 ? ? max16998a 100 ?? ? max16998b 50 ?? ? max16998d 75 ?? ? selector guide ordering information 19-4000; rev 2; 8/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. +denotes a lead(pb)-free/rohs-compliant package. /v denotes automotive qualified part. pin configurations appear at end of data sheet. ?ax is a registered trademark of maxim integrated products, inc.
max16997/max16998 high-voltage watchdog timers with adjustable timeout delay 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = 14v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . (all pins referenced to gnd, unless otherwise noted.) in, enable ............................................................-0.3v to +45v wdi, reset , en .....................................................-0.3v to +20v resetin .................................................................-0.3v to +20v srt, swt................................................................-0.3v to +12v maximum current (all pins).................................................30ma continuous power dissipation (t a = +70?) 8-pin ?ax (derate 4.8mw/? above +70?) ..........387.8mw junction-to-case thermal resistance ( jc ) (note 1) ......42?/w junction-to-ambient thermal resistance ( ja ) (note 1).....206.3?/w operating temperature range (t a ) ..................-40? to +125? junction temperature (t j ) ...............................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units operating voltage range v in 5.0 40.0 v t a = -40? to +85? 18 30 supply current i in t a = -40? to +125? 18 60 ? swt ramp current i ramp_swt v swt = 1.0v 450 500 550 na srt ramp current i ramp_srt v srt = 1.0v 410 500 600 na swt/srt ramp threshold voltage v ramp 1.115 1.235 1.363 v reset timer v resetin rising 1.135 1.255 1.383 power-on reset input threshold voltage v pon v resetin falling 1.115 1.235 1.363 v resetin input leakage current i lpon v resetin = 2v 0.1 ? reset asserted, i sink = 1ma 0.9 v in = 1.1v, i sink = 160?, reset asserted 0.4 reset output low voltage v olrst reset asserted, i sink = 0.4ma 0.4 v reset leakage current i lkgr v reset = 20v, reset not asserted 0.1 ? enable output low voltage v olen enable asserted, i sink = 5ma 0.4 v enable leakage current i lkge v enable = 14v, enable not asserted 0.1 ? minimum reset timeout period t resetmin c srt = 390pf (note 3) 1 ms reset timeout period t reset c srt = 2000pf (note 3) 5 ms maximum reset time period t resetmax c srt = 47nf 116.09 ms reset to enable delay t redl 1.5 ? resetin to reset delay t rrdl resetin falling below v pon to reset falling edge 1s
max16997/max16998 high-voltage watchdog timers with adjustable timeout delay _______________________________________________________________________________________ 3 note 2: r reset and r enable are external pullup resistors for open-drain outputs. connect r reset and r enable to a minimum 2.5v voltage. connect r reset to a maximum voltage of 18v and connect r enable to a maximum voltage of 28v. note 3: calculated based on v ramp = 1.235v and i ramp = 500na. note 4: wdi pulses narrower than 1? will be ignored. wdi pulses wider than 6.5? will be recognized. note 5: not production tested, guaranteed by design. parameter symbol conditions min typ max units watchdog timer v ih 2.25 wdi input threshold v il 0.9 v wdi input hysteresis wdi hyst 200 mv wdi minimum pulse width t wdimin (note 4) 6.5 ? wdi input current i wdi wdi = 0 or 14v 0.1 ? minimum watchdog timeout t wpmin c swt = 680pf (note 3) 6.8 ms watchdog timeout period t wp c swt = 1200pf (note 3) 12 ms maximum watchdog timeout t wpmax c swt = 22nf 217.36 ms max16998b 45 50 55 watchdog window d wdi max16998d 67.5 75 82.5 %t wp wdi to enable output delay start from wdi third wrong trigger 100 ? reset pullup resistor supply voltage (note 5) 2.25 2.5 18.00 v enable pullup resistor supply voltage (note 5) 2.25 2.5 28.00 v electrical characteristics (continued) (v in = 14v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 2) reset timeout period vs. c srt max16997/98 toc01 c srt (nf) reset timeout period (ms) 100 10 1 1 10 100 1000 10,000 0.1 0.1 1000 i ramp = 500na watchdog timeout period vs. c swt max16997/98 toc02 c swt (nf) watchdog timeout period (ms) 100 10 1 10 100 1000 10,000 1 0.1 1000 i ramp = 500na supply current vs. supply voltage max16997/98 toc03 supply voltage (v) supply current ( a) 40 30 10 20 12 14 16 18 22 20 24 26 10 050 reset and enable not asserted typical operating characteristics (c swt = c srt = 1500pf, t a = +25?, unless otherwise noted.)
max16997/max16998 high-voltage watchdog timers with adjustable timeout delay 4 _______________________________________________________________________________________ typical operating characteristics (continued) (c swt = c srt = 1500pf, t a = +25?, unless otherwise noted.) supply current vs. temperature max16997/98 toc04 temperature ( c) supply current ( a) 110 95 65 80 -10 5 20 35 50 -25 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 20.0 15.0 -40 125 reset and enable not asserted resetin/en threshold voltage vs. temperature max16997/98 toc05 temperature ( c) resetin/en threshold voltage (v) 110 95 65 80 -10 5 20 35 50 -25 1.13 1.15 1.18 1.20 1.23 1.25 1.28 1.30 1.33 1.35 1.10 -40 125 rising falling resetin/en threshold voltage vs. supply voltage max16997/98 toc06 supply voltage (v) resetin/en threshold voltage (v) 36 32 24 28 12 16 20 8 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.00 440 rising falling resetin to reset delay vs. temperature max16997/98 toc07 temperature ( c) resetin to reset delay ( s) 110 95 -25 -10 5 35 50 65 20 80 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 -40 125 resetin from 2v to 0v 100mv overdrive 50mv overdrive resetin/watchdog period vs. supply voltage max16997/98 toc08 supply voltage (v) reset/watchdog timeout period (ms) 36 32 8 12 16 24 20 28 1 2 3 4 5 6 7 8 0 440 watchdog timeout period (c swt = 680pf) reset timeout period (c srt = 680pf) resetin/watchdog period vs. supply voltage max16997/98 toc09 supply voltage (v) reset/watchdog timeout period (ms) 36 32 24 28 12 16 20 8 20 30 40 50 60 70 80 90 100 110 10 440 watchdog timeout period (c swt = 10nf) reset timeout period (c srt = 10nf) i ramp vs. temperature max16997/98 toc10 temperature ( c) i ramp (na) 110 95 65 80 -10 5 20 35 50 -25 475 480 485 490 495 500 505 510 515 520 470 -40 125 reset output voltage vs. sink current max16997/98 toc11 sink current (ma) reset output voltage (v) 2.5 2.0 1.5 1.0 0.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 03.0 enable output voltage vs. sink current max16997/98 toc12 sink current (ma) enable output voltage (v) 25 20 5 10 15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 030
max16997/max16998 high-voltage watchdog timers with adjustable timeout delay _______________________________________________________________________________________ 5 pin description pin max16997a max16998a/b/d name function 1 1 in power-supply input. bypass in to gnd with a 0.1? capacitor. 2en high-impedance input to the enable comparator. depending on the voltage level at en, the internal watchdog timer is turned on or off (see the en input section). 3, 7 n.c. no connection. not internally connected. 44swt watchdog timeout adjustment input. connect a capacitor between swt and gnd to set the basic watchdog timeout period. connect swt to ground to disable the watchdog timer function. see the selecting the watchdog timeout capacitor section. 5 5 gnd ground 6 6 wdi watchdog input. max16997a/max16998a (timeout watchdog): two consecutive wdi falling edges must occur at wdi within the watchdog timeout period or reset asserts. the watchdog timer clears when a falling edge occurs on wdi or whenever reset is asserted. enable asserts if three consecutive watchdog timeout periods have expired without a falling edge at wdi. wdi is a high-impedance input. leaving wdi unconnected will cause improper operation of the watchdog timer. max16998b/d (window watchdog): wdi falling transitions within periods shorter than the closed window width or longer than the basic watchdog timeout period force reset to assert low for the reset timeout period. the watchdog timer begins to count after reset is deasserted. the watchdog timer clears when a wdi falling edge occurs or whenever reset is asserted. enable asserts if three consecutive watchdog timeout periods have expired without a falling edge at wdi. wdi is a high-impedance input. leaving wdi unconnected will cause improper operation of the watchdog timer. 88 enable open-drain enable output. enable asserts when three consecutive wdi faults occur. enable remains low until three consecutive good wdi falling edges occur. enable does not assert if the voltage at resetin (en) is below its threshold. these devices are guaranteed to be in correct enable output logic state when v in remains greater than 1.1v. 2 resetin reset input. high-impedance input to the reset comparator. when v resetin falls below 1.235v, reset asserts. reset remains asserted as long as v resetin is low and for the reset timeout period after resetin goes high. connect v resetin to the center point of an external resistive divider to set the threshold for the externally monitored voltage. connect resetin to a defined voltage logic-level. 3 srt reset timeout adjustment input. connect a capacitor between srt and gnd to set the reset timeout period. see the selecting the reset timeout capacitor section. ? reset open-drain reset output. reset asserts whenever resetin drops below the selected reset threshold voltage (v pon ). reset remains low for the reset timeout period after all reset conditions are removed, and then goes high. reset asserts for a period of t reset whenever a wdi fault occurs. connect reset to a pullup resistor connected to a voltage higher than 2.5v (typ).
max16997/max16998 high-voltage watchdog timers with adjustable timeout delay 6 _______________________________________________________________________________________ functional diagram in resetin (max16998) en (max16997) wdi reset enable swt srt (max16998) v bg v bg i ramp preg buffer max16997a/ max16998a/b/d logic gnd v bg i ramp max16997/max16998
max16997/max16998 high-voltage watchdog timers with adjustable timeout delay _______________________________________________________________________________________ 7 timing diagrams v en v hyst t wp initial t wp initial = watchdog timeout period x 8 t wp = watchdog timeout period t wdi = wdi trigger period 3 consecutive t wp without trigger enable goes low 3 consecutive watchdog trigger (wdi) enable goes active high t wp t wd t wp t wp 1 2 312 3 t wp t wp t wdi t wdi t wdi t wdi v pon wdi enable figure 1. max16997a timing diagram v resetin v hyst t reset = reset timeout period t wp = watchdog timeout period t wdi = wdi trigger period 3 consecutive resets enable goes active low 3 consecutive watchdog trigger (wdi) enable goes active high 1 1 2 2 3 3 t wp t wdi t wp t wp t wp t wdi t wdi t wdi t reset v pon wdi enable reset figure 2. max16998a timing diagram
max16997/max16998 high-voltage watchdog timers with adjustable timeout delay 8 _______________________________________________________________________________________ timing diagrams (continued) v resetin v hyst proper watchdog trigger resets the internal enable counter t reset = reset timeout period t ow = t open window t cw = t closed window t wp = t cw + t ow t wdi = wdi trigger period 3 consecutive resets enable goes active low 3 consecutive watchdog trigger (wdi) enable goes active high t wp 1 2 3 12 3 t wdi t reset t ow t cw t wp t wp t wp t wdi t wdi t wdi v pon wdi enable reset figure 3. max16998b/d timing diagram v hyst t ow t = 0 t cw t wp t reset t cw t wdi t wp t cw t wdi t wp t wp enable does not get asserted if the voltage at resetin is below its threshold. the watchdog timer clears whenever reset is asserted. t rrdl t wdi t wdi t wdi t wdi t wdi t wdi t wdi t wdi v resetin v pon wdi 1.1v v in = enable reset t reset t reset figure 4. resetin, reset , v in , enable , and wdi voltage monitoring
max16997/max16998 high-voltage watchdog timers with adjustable timeout delay _______________________________________________________________________________________ 9 detailed description the max16997/max16998 are ? supervisory circuits for high-input-voltage and low-quiescent-current appli- cations. these devices improve system reliability by monitoring the sub-system for software code execution errors. the max16997a/max16998a/b/d detect down- stream circuit failures, and provide switchover to redundant circuitry. these devices provide complete adjustability for reset and watchdog functions. the max16998a/b/d generate two output signals, reset and enable , that depend on the voltage level at resetin and the signal at wdi. reset asserts whenever resetin drops below the selected reset threshold voltage. reset remains low for the reset timeout period after all reset conditions are deasserted, and then goes high. reset also asserts for a period of t reset whenever a wdi fault occurs. the max16997a generates one output signal ( enable ) based on the voltage level at en and the signal at wdi. the max16997a/max16998a provide watchdog time- out adjustability with an external capacitor. the max16998a asserts reset when two consecutive wdi falling edges do not occur within the watchdog timeout period. this device also asserts enable if three con- secutive watchdog timeout periods have elapsed with- out a falling edge at wdi. enable remains low until three consecutive good wdi falling edges occur. enable does not assert if the voltage at resetin (en) is below its threshold. for the max16997a, the watch- dog timer starts timing if the voltage at en is higher than a preset threshold level. each time the voltage at en rises from below to above the preset threshold volt- age, the initial watchdog timeout period is 8 times the normal watchdog timeout period (t wp ). other than described above, the max16997a behaves the same as the max16998a. the max16998b/max16998d contain a window watch- dog timer that looks for activity outside an expected window of operation. the window size is factory-set to 50% (max16998b) or 75% (max16998d) of the adjust- ed watchdog timeout period. reset output ( reset ) (max16998a/b/d) the reset output is typically connected to the reset input of the ? to start or restart it in a known state. the max16998a/b/d provide an active-low open-drain reset logic to prevent code execution errors. for the max16998a/b/d, reset asserts whenever resetin drops below the selected reset threshold volt- age (v pon ). reset remains low for the reset timeout period after resetin exceeds the selected threshold voltage, and then goes high. the max16998a asserts reset for a period of t reset when two consecutive wdi falling edges do not occur within the adjusted watchdog timeout period. the max16998b/d also assert reset for a period of t reset when a wdi falling edge does not occur within the open window period. anytime reset asserts, the watchdog timer clears. at the end of the reset timeout period, reset goes high, and the watchdog timer is restarted from zero (see the selecting the watchdog timeout capacitor section). enable output ( enable ) if the ? fails to operate correctly (e.g., the software execution is stuck in a loop), wdi does not trigger any more and reset pulls low, resetting the ?. if the ? does not work properly in the next loop either, the device asserts reset again. after three watchdog timeout periods elapse with no falling edges at wdi, enable asserts and flags a backup circuit that can take over the operation. enable remains low until three consecutive wdi falling edges with periods shorter than the watchdog timeout occur. enable does not assert if the voltage at resetin (en) is below its threshold. these devices are guaranteed to be in correct enable output logic state when v in remains greater than 1.1v. power-on/power-off sequence figure 5 shows the power-up and power-down sequence for reset and enable for the max16998a/b/d. on power-up, once v in reaches 1.1v, reset goes logic-low. as resetin rises, reset remains low. when resetin rises above v pon , the reset timer starts and reset remains low. when the reset timeout period ends, reset goes high. on power-down, once resetin goes below v pon , reset goes low and remains low until v in drops below 1.1v. figure 6 shows the detailed power-up sequence for the max16998a/b/d.
max16997/max16998 high-voltage watchdog timers with adjustable timeout delay 10 ______________________________________________________________________________________ v hyst t reset t wp t cw t wdi t wp t cw t wdi t wp the three consecutive reset could be caused by three timeouts as shown here or by three wdi falling edge outside the open window, or a combination of any reset conditions except v resetin drops too low. t ow t = 0 t cw t wp t reset t reset t reset t wdi t wdi t wdi t wdi t wdi t wdi t wdi t wdi v resetin v in v in = 1.1v v pon wdi enable reset reset wdt clears and starts counting from o wdi t wp t wp figure 5. power-on reset and power-down reset for the max16998a/b/d v hyst v in = 1.1v v pon v in = v enable v resetin v reset t reset figure 6. detailed power-up sequence for the max16998a/b/d
resetin input (max16998a/b/d) the max16998a/b/d monitor the voltage at resetin using an adjustable reset threshold, set with an external resistive divider (see figure 7). reset asserts when v resetin is below 1.235v. use the following equations to calculate the externally monitored voltage (v cc ). where v th is the desired reset threshold voltage, and v pon = 1.235v. to simplify the resistor selection, choose a value for r 2 (< than 1m ? ) and calculate r 1 . en input the max16997a provides a high-impedance input (en) to the enable comparator. based on the voltage level at en, the watchdog timer is turned on or off. the watch- dog timer starts timing if the voltage level at en is high- er than a preset threshold voltage (v pon ). each time the voltage at en rises from below to above the preset threshold voltage, the initial watchdog timeout period is 8 times the normal watchdog timeout period (t wp ). watchdog timer max16997a the watchdog circuit monitors the ?? activity. for the max16997a, the watchdog timer starts timing once the voltage at en is higher than a preset threshold voltage. enable asserts if three consecutive watchdog timeout periods have elapsed without a falling edge at wdi. enable remains low until three consecutive wdi falling edges with periods shorter than the watchdog timeout period occur. each time the voltage at en rises from below to above the preset threshold voltage, the first watchdog timeout period extends by a factor of 8 (8 x t wp ). if a wdi falling edge occurs during that time, then the watchdog time- out period is immediately switched over to a single t wp . if no watchdog falling edge occurs during this pro- longed watchdog timeout period, enable goes low at the end of this period and stays low. after this, the first falling edge at wdi switches the watchdog timeout period to a single t wp . see figure 1. the max16997a watchdog timeout period (t wp ) is adjustable by a single capacitor at swt. max16998a the max16998a asserts reset when two consecutive wdi falling edges do not occur within the adjusted watchdog timeout period (t wp ). reset remains assert- ed for the reset timeout period (t reset ) and then goes high. this device also asserts enable if three consec- utive watchdog timeout periods have elapsed without a falling edge at wdi. enable remains low until three consecutive wdi falling edges with periods shorter than the watchdog timeout period occur (see figure 2). the internal watchdog timer is cleared by a reset ris- ing edge or by a falling edge at wdi. the watchdog timer remains cleared while reset is asserted; as soon as reset is released, the timer starts counting. wdi falling edges are ignored when reset is low. if no wdi falling edge occurs within the watchdog timeout period, reset immediately goes low and stays low for the adjusted reset timeout period. max16998b/d the max16998b/d have a windowed watchdog timer. the watchdog timeout period (t wp ) is the sum of a closed window period (t cw ) and an open window period (t ow ). if the ? issues a wdi falling edge within the open window period, reset stays high. once a wdi falling edge occurs within the closed window period, reset immediately goes low and stays low for the adjusted reset timeout period (see figure 3). if no wdi falling edge occurs within the watchdog timeout period, reset immediately goes low and stays low for the adjusted reset timeout period. the open window size is factory-set to 50% of the watchdog timeout period for the max16998b and 75% for the max16998d. figure 8 shows a wdi falling edge identified as a good or a bad wdi signal edge. in case 1, the wdi falling edge occurs within the closed window period and is considered a bad wdi falling edge (early fault); therefore, it asserts reset . case 2 also shows another fault. in this case, no rr v v th pon 12 1 =? ? ? ? ? ? ? vv r r th pon =+ ? ? ? ? ? ? 1 2 1 max16997/max16998 high-voltage watchdog timers with adjustable timeout delay ______________________________________________________________________________________ 11 max16998a/b/d resetin v in v cc r1 r2 figure 7. setting resetin voltage for the max16998a/b/d
max16997/max16998 wdi falling edge occurs within the watchdog timeout period (t wp ) and is considered a late fault that asserts reset . in case 3, the wdi falling edge occurs within the open window period and is considered a good wdi sig- nal falling edge. in this case, reset stays high. in case 4, the wdi falling edge occurs within the indeterminate region. in this case, the reset state is indeterminate. these devices assert enable after three consecutive bad wdi falling edges. enable returns high after three consecutive good wdi signal falling edges (see figure 3). either a rising edge at reset or a falling edge at wdi clears the internal watchdog timer. the watchdog timer remains cleared while reset is asserted. the watch- dog timer begins counting when reset goes high. wdi falling edges are ignored when reset is low. applications information selecting the reset timeout capacitor the reset timeout period is adjustable to accommodate a variety of ? applications. adjust the reset timeout period (t reset ) by connecting a capacitor (c srt ) between srt and ground. see the reset timeout period vs. c srt graph in the typical operating characteristics . calculate the reset timeout capacitance using the equation below: where v ramp is in volts, t reset is in seconds, i ramp is in na, and c srt is in nf. leakage currents and stray capacitance (e.g., a scope probe, which induces both) at srt may cause errors in the reset timeout period. if precise time control is required, use capacitors with low leakage current and high stability. selecting the watchdog timeout capacitor the watchdog timeout period is adjustable to accom- modate a variety of ? applications. with this feature, the watchdog timeout can be optimized for software execution. the programmer determines how often the watchdog timer should be serviced. adjust the watch- dog timeout period (t wp ) by connecting a capacitor (c swt ) between swt and gnd. for normal mode operation, calculate the watchdog timeout capacitance using the following equation: where v ramp is in volts, t wp is in seconds, i ramp is in na, and c swt is in nf. see the watchdog timeout period vs. c swt graph in the typical operating characteristics . for the max16998b/max16998d, the open window size is factory-set to 50% (max16998b) or 75% (max16998d) of the watchdog period. leakage currents and stray capacitance (e.g., a scope probe, which induces both) at swt may cause errors in the watchdog timeout period. if precise time control is required, use capacitors with low leakage current and high stability. to disable the watch- dog timer function, connect swt to ground and connect wdi to either the high- or low-logic state. ct i v swt wp ramp ramp = 4 ct i v srt reset ramp ramp = high-voltage watchdog timers with adjustable timeout delay 12 ______________________________________________________________________________________ t wdimin reset rising edge t wdimax t wp (50% or 75%) x t wp case 1 (fast fault) case 2 (slow fault) case 3 (good wdi) case 4 (indeterminate) closed window open window indeterminate figure 8. the max16998b/d window watchdog diagram
interfacing to other voltages for logic compatibility as shown in figure 9, the open-drain reset output can operate in the 2.5v to 18v range. this allows the device to interface a ? with other logic levels. wdi glitch immunity for additional glitch immunity, connect an rc lowpass filter as close as possible to wdi (see figure 10). for example, for glitches with duration of 1?, a 12k ? resistor and a 47pf capacitor will provide immunity. layout considerations srt and swt are connected to internal precision cur- rent sources. when developing the layout for the appli- cation, minimize stray capacitance attached to srt and swt as well as leakage currents that can reach those nodes. srt and swt traces should be as short as possible. route traces carrying high-speed digital signals and traces with large voltage potentials as far from srt and swt as possible. leakage currents and stray capacitance (e.g., a scope probe, which induces both) at these pins may cause errors in the reset and/or watchdog timeout period. when evaluating these parts, use clean prototype boards to ensure accurate reset and watchdog timeout periods. resetin is a high-impedance input and a high-imped- ance resistive divider (e.g., 100k ? to 1m ? ) sets the threshold level. minimize coupling to transient signals by keeping the connections to this input short. any dc leakage current at resetin (e.g., a scope probe) causes errors in the programmed reset threshold. typical operating circuits reset remains asserted as long as resetin is below the regulated voltage and for the reset timeout period after resetin goes high to assure that the monitored ldo voltage is settled. then, the ? starts operating and triggers wdi. if the ? fails to operate correctly (e.g., the software execution is stuck in a loop), the wdi signal does not trigger the watchdog timer any more, and reset is pulled low, resetting the ?. if the ? does not work properly in the next loop either, the device asserts reset again. after three watchdog timeout periods with no wdi falling edges, enable asserts and flags backup or safety circuits that take over the operation. max16997/max16998 high-voltage watchdog timers with adjustable timeout delay ______________________________________________________________________________________ 13 max16998a/b/d reset reset gnd gnd 5v to 40v 2.5v to 18v in v cc p n 10k ? max16998a/b/d wdi i/o gnd gnd in v cc r c p figure 9. interfacing to other voltage levels figure 10. additional wdi glitch immunity circuit
max16997a enable reset 5v backup circuitry, peripheral backup circuitry flags separate watchdog en swt gnd in v batt v cc r1 r2 watchdog ldo 5v regulator i/o gnd c i/o wdi figure 12. max16997a application diagram max16997/max16998 high-voltage watchdog timers with adjustable timeout delay 14 ______________________________________________________________________________________ max16998a/b/d enable en reset srt backup circuitry, peripheral 5v regulator resetin swt gnd in v batt v cc v cc r1 r2 reset i/o gnd c wdi figure 11. max16998a/b/d switch over to backup circuitry
max16997/max16998 pin configurations top view 1 2 3 4 8 7 6 5 enable n.c. wdi gnd swt n.c. en in max16997a max + 1 2 3 4 8 7 6 5 enable reset wdi gnd swt srt resetin in max16998a/b/d max + chip information process: bicmos high-voltage watchdog timers with adjustable timeout delay ______________________________________________________________________________________ 15 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 8 ?ax u8-1 21-0036
max16997/max16998 high-voltage watchdog timers with adjustable timeout delay maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/08 initial release 1 4/09 added bullet to features section, revised electrical characteristics table. 1, 2, 3 2 8/09 added automotive qualified parts. 1

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